Port amd64 SIMD libc optimizations to riscv64
Student: StrahinjaStanisic (strajabot@FreeBSD.com)
Mentor: RobertClausecker (fuz@FreeBSD.com), EdMaste (emaste@FreeBSD.com)
Project description
The goal of the project is to port the SIMD optimized routines written for amd64 to riscv64. This will be accomplished using SWAR techniques. Because the code will only depend on the base integer ISA, the optimizations will result in a performance increase on all riscv64 systems.
Deliverables
In no particular order, the functions that will be implemented in RISC-V assembly:
memset
memmove
memcpy
memcmp
memccpy
memchr
memrchr
strlen
stpcpy
stpncpy
strcat
strchrnul
strcmp
strcspn
strlcpy
strncmp
strrchr
strspn
timingsafe_bcmp [1]
timingsafe_memcmp [1]
[1] Need to be implemented to run in constant time
The following libc functions will also benefit from the assembly rewrite:
bcmp -> from memset
bcopy -> from memmove
bzero -> from memset
strcpy -> from stpcpy
strlcat -> from memchr, strlcpy
strncat -> from strlen, memccpy
strncpy -> from stpncpy
strnlen -> from strcspn
strsep -> from strcspn
Milestones
(TODO: More info)
- May 27th: Start of coding
- June 3rd: Second week
- July 8th - July 12th: Mid-term Evaluations
- August 19th - August 26th: Final week
Test Plan
Code will be tested using the available FreeBSD tests on a RISC-V development board (HF105-000). Additional tests will be written if needed. Performance will be measured using strperf (https://github.com/clausecker/strperf).
The Code
https://github.com/strajabot/freebsd-src
Notes
I will posting updates on my blog while I work on the project (https://strajabot.com)
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